TQM:Electronics & Communication Engineering 7th semester notes

SUBJECT: MG 1401-TOTAL QUALITY MANAGEMENT

SET-3

PART-A

1] Define quality.

A] Fitness for intended use; Conformance to specifications; Meeting or exceeding customer expectations, etc.

2] What do you understand by quality statement?

A] It includes the vision, mission, and quality policy statements. They are part of the strategic planning process.

3] What is cross functional team?

A] It is a team comprising of members from different functional area such as engineering, marketing, accounting, production, quality, human resources, etc. This type of team breaks down functional area boundaries.

4] Expand 5S.

A] Seiri, Seiton, Seiso, Seiketsu, and Shitsuke.

5] List out various measures of dispersion in SPC.

A] Range, Standard Deviation, and Variance.

6] What is Six Sigma?

A] Six sigma is a rigorous concept of applying SPC to control defects in products/processes to 3.4 parts per million (ppm) as against 0.27% (2,700ppm) defects in the traditional three sigma approach. Hence the application of six sigma concept means controlling variations and thereby defects closer to the level of zero defects.

7] What is Kaizen?

A] Kaizen is a Japanese term which means ‘continuous improvement’. It is based on the belief that virtually any aspect of an operation or process can be improved and the people most closely associated with it are in the best position to identify the changes to be made.

8] What is Taguchi Quality Loss Function?

A] Taguchi worked in terms of quality loss rather than quality. He used loss function to measure quality. The loss function is defined ad “loss imparted to society by a product during its life cycle”, i.e. the costs incurred in the production process as well as the costs encountered during use by the customer.

9] What are the objectives of TPM?

A] Maintaining equipment for life; maintaining and improving equipment capacity; using support from all areas of operation; encouraging inputs from all employees.

10] What is the need for quality systems in an organization?

A] They promote the growth of international trade by facilitating harmonious interactions between suppliers and customers located in diverse locations globally.

PART-B

11[a] List out the barriers to TQM implementation.

A] Explain the various likely barriers  to effective TQM implementation such as Lack of management commitment, Inability to change organizational culture, etc.

11[b] Discuss the dimensions of quality with examples.

A] Discuss the various dimensions of product quality such as Performance, Features, Usability, etc. and the various dimensions of service quality such as Time, Timeliness, Completeness, etc. supported by appropriate examples.

12[a] Explain the actions that an organization should take to handle customer complaints.

A] Explain the characteristics of dissatisfied/unhappy/lost customers, the importance of retaining customers, and actions an organization can take to handle customer complaints.

12[b] Explain the importance of customer satisfaction.

A] Explain the meaning of internal and external customers, customer perception of quality, and the benefits of customer retention and customer loyalty.

13[a] Explain the different types of control charts used for problem solving.

A] Discuss the salient features of control charts in general and the specific application of X bar chart, R chart, p chart, np chart, c chart, and u chart with sketches.

13[b] Explain the use of the seven new management tools for managing quality.

A]  Explain the salient features and usage of Affinity diagram, relationship diagram, Tree diagram, Matrix diagram, Prioritization matrix, Process decision program chart, and Activity network diagram.

14[a] Explain the QFD process in detail.

A] Explain about QFD, discuss about the use of HOQ as a tool for implementing QFD, and explain the six components of the House of Quality through any example.

14[b] Explain the different steps involved in FMEA.

A] Give a brief introduction to the topic Failure Modes and Effects Analysis, explain the four stages in conducting FMEA, and the various components of the FMEA document.

15[a] Discuss the method of conducting quality audit for ISO 9000 certification.

A] Give the definition of the term ‘quality audit’,  explain the stages in conducting quality audit, and the checklists for conducting audit.

15[b] Explain the requirements of Environmental Management Systems.

A] Explain the need for ISO 14000 as an Environmental Management System, the rationale behind its use, the various organizational and product evaluation standards, and the major elements of the EMS standards.

VLSI:Electronics & Communication Engineering 7th semester notes

VLSI

DEPARTMENT OF ECE

EC1401: VLSI DESIGN

PART-A

UNIT I: CMOS TECHNOLOGY

1. What is latch-up?

·         Latch-up is the shorting of the VDD & VSS lines in CMOS fabrication process due to parasitic circuit effect.

·         Latch-up results in chip self-destruction or system failure.

2. How is a capacitor created in CMOS fabrication process?

·         Capacitors are created in the CMOS fabrication process by adding at least one extra layer of polysilicon.

·         Between the two polysilicon layers, a second thin-oxide layer is required.

·         Diagram

3. List the materials used for masks in IC technology.

·         Photoresist

·         Polysilicon

·         Silicon dioxide

·         Silicon nitride

4. Draw the circuit of a CMOS 2 input NAND gate.

Refer figure 1.6 in Weste

5. What are the advantages of twin tub process?

·         Used for protection against latch-up

·         Provides separate optimization of p-type & n-type transistors

6. How is resistor created in CMOS fabrication process?

·         If Polysilicon is left undoped, it is highly resistive. This property is used to build resistors.

·         A resistive metal such as nichrome me be added to produce high value & high quality resistors.

·         The resistor accuracy might be improved by laser trimming the resulting resistors on each chip to some predetermined test specification.

7. What is BiCMOS?

·         BiCMOS is the combination of bipolar & CMOS transistors.

·         To reduce the delay times of the highly loaded signals (microprocessor busses) and to provide better performance for analog functions the bipolar devices (npn or pnp) can be added to MOS transistors or vice versa.

8. What are the advantages of SOI process?

·         There is no latch-up

·         There are no body-effect problems

·         No field-inversion problems

·         Lower substrate capacitances provide the possibility for faster cirecuits.

9. What is the objective of the layout rules?

·         To obtain a circuit with optimum yield in as small an area as possible without compromising reliability of the circuit.

10. What are the types of layout design rules?
• Micron rule
• Lambda based rule

11. What is guard ring?

·         p⁺ diffusion in the P-substrate and n⁺ diffusion in the n-well are called guard rings that are used to collect injected minority carriers.

·         When they are implemented in a structure, the n⁺ guard ring must be tied to VDD and the p⁺ guard ring must be connected to VSS.

·         Guard rings must be included in the fabrication process to prevent I/O latch-up.

12. What is scribe line?

·         The scribe line is a specifically designed structure that surrounds the completed chip and is the point at which the chip is cut with a diamond saw.

·         The construction of the scribe line varies from manufacturer to manufacturer.

13. What is passivation or overglass?

This is a protective glass layer that covers the final chip. Openings are required at pads and any internal test points.

14. List the two techniques that can be used to prevent latch-up

Latch-up resistant CMOS process

Layout techniques

15. What are the types of oxidation?

Wet Oxidation: The oxidizing atmosphere contains water vapor

Dry Oxidation: The oxidizing atmosphere is pure oxygen

16. What are the advantages of EBL pattern generation?

·         EBL: Electron Beam Lithography

·         Patterns are derived directly from digital data

·         There are no intermediate hardware images

·         Different patterns may be accommodated in different sections of the wafer without difficulty.

·         Changes to patterns can be implemented quickly.

17. What are the types of etching process?

Isotrophic etch

Fully anisotrophic etch

Preferential etch

18. What are the types of interconnect?

·         Metal interconnect

·         Polysilicon/Refractory interconnect

·         Local interconnect

19. What is a thinox ?

·         Thinox is an active mask formed which defines the areas where thin oxide are needed to implement transistor gates and allow implantation to form P or N-type diffusions for transistor source/drain regions. 

20. How is the channel stop implant made?

·         Channel stop implant is made by doping the P-substrate in areas where there are no N-transistors P⁺ using a photo resist mask.

                               

21. List the four main CMOS technologies

i. N-well process

ii.                P-well process

iii.               Twin-tub process

iv.               Silicon on insulator.

UNIT II: MOS TRANSISTOR THEORY

1. Draw the structure of a nmos enhancement transistor.

     Fig.2.3 pg 43

2. Draw the characteristics of a n- channel & p – channel enhancement transistor.

          Fig 2.2 pg 42 Weste

3. What are the advantages of SiO₂  as a dielectric.

SiO₂   has a relatively low loss & high dielectric strength, thus application of high gate fields is possible.

4. State  the 3 modes involved in the operation of an enhancement transistor

1. Accumulation mode 2.Depletion mode 3. Inversion mode.

5. What is a field induced junction?

In a pn junction the n- type conductivity is brought about by a metallurgical process, ie the electrons are introduced into the semiconductor by the introduction of donor ions. In an inversion layer substrate junction, the n- type layer is induced by the electric field E applied to the gate .Thus this junction instead of being a metallurgical junction is a field induced junction.

6. What are the factors that influence the drain current.

• The distance between source and drain
• The channel width
• The threshold voltageVt
• The thickness of the gate – insulating oxide layer
• The dielectric constant of the gate insulator
• The carrier(electron or hole) mobility, µ.
6. Define cut – off and saturated regions in the characteristics of an MOS transistor.

Cut – off current flow is essentially slow.

Saturated region – Channel is strongly inverted and the drain current flow is independent of the drain – source voltage.

8. Define threshold voltage and state the parameters on which it is dependent on.

Vt can be defined as the voltage applied between gate & source of an MOS device below which Ids effectively drops to zero. It is a function of 

• Gate conductor material
• Gate insulation material
• Gate insulator thickness  - channel doping
• Impurities at the silicon insulator interface
• Voltage between the source and the substrate,Vsb.
8. Define Body effect.

·         The threshold voltage Vt is not constant with respect to the voltage difference between the substrate and the source of the MOS transistor.

·         So, when several MOS devices are connected in series, the threshold voltage is increased due to voltage difference between the substrate and the source. This effect of body or substrate voltage is called body effect.

10. What is channel length modulation?

·         When an MOS device is in saturation, the effective channel length is decreased such that, L_eff = L - L_short .

Where L_short  = √ 2(ε_si /qNa) (Vds – (Vgs – Vt))

·         The reduction in channel length increases the W/L ratio, thereby increasing β as the drain voltage increases.

11. Draw the small signal model of a MOS transistor.

          Fig 2.10 Pg 60

12. Define noise margin. Illustrate how it can be obtained from the transfer characteristics of a CMOS Inverter.

Noise margin is a parameter that allows us to determine the allowable noise voltage on the input of a gate so that the output will not be affected. The 2 common parameters are N_MH & N_ML Where

N_ML = | V_ILmax – V_OLmax| and N_MH = | V_OHmin – V_IHmin|

           V_IHmin=minimum HIGH input voltage

          V_ILmax = maximum LOW i/p voltage

V_OHmin = minimum HIGH o/p voltage

V_OLmax = maximum LOW o/p voltage

13. What is a transmission  gate.

A transmission  gate consists of an n- channel transistor and a p – channel transistor with separate gate connections and common source and drain connections. It gives good transmission of both logic 1 and logic 0.

         

14. Why is the transmission of logic 1 degraded as it passes through a nmos pass transistor.

When S = 1 (Vdd) , and Vin = 1 the pass transistor begins to conduct and charges the CL  towards Vdd.Initially Vin is at ahigher potential than Vout, the current flows through the device. As voltage ot the load approaches Vdd – Vtn, the n- device begins to turn – off. Vtn  is the n- transistor body effected threshold .. Thus the transmission of logic 1 is degraded.

15. What is a tristate  inverter.

A tristate inverter is got by cascading a transmission gate with an inverter. When c = 0 and –c = 1, the output of the inverter is in a tristate condition.

16. Draw the structure & symbol of a CMOS tri - state inverter.

     Fig 2.37 PG 91. Weste

17. Write the equation for total static power dissipation.

        n

Ps = ∑ leakage current X supply voltage

                   1

                   n = no: of devices.

18. Define rise time( t_r ).

T_r is the time for a waveform to rise from 10% to 90% of its steady state value.

19. Define fall time ( t_f)

Time for a waveform to fall from 90% to 10% of its steady state value.

20. Define delay time,t_d.

Time difference between input transition and 50% output level .This is the time taken for a logic transition to pass from input to output. Fig 4.18 (a) Page 207 Weste.

UNIT III: SPECIFICATION USING VERILOG HDL

1. Write the syntax for switch primitive instantiation.

·         Syntax: switch_name instance_name(output, data, control_input);

·         Example:  nmos n1 (out, data, control);

pmos p1 (out, data, control);

cmos c1 (out, data, ncontrol, pcontrol);

2. List out different data types in verilog.

·         Net type: It represents a physical connection between structural elements. Ex: wire

·         Register type: It represents an abstract data storage element. It is assigned values only within an always statement or an initial statement. Ex: reg

3. Give the symbol, Truth table and syntax of bufif1.

Truth table:

	Control input
Input		0	1	x	Z
	0	z	0	L	L
	1	z	1	H	H
	x	z	x	x	x
	z	z	x	x	x

Syntax:    bufif1 n1 (out, input, control);

Symbol:

4. Give the structural coding of an Half adder

module HA (a, b, sum, carry)

input a, b;

output sum, carry;

xor (sum, a, b);

                        and (carry, a, b);

              endmodule

5. What are the types of modeling in verilog?
• Structural
• Data flow
• Behavioral
6. What is HDL?

·         HDL: Hardware Description Language

·         HDL is a standard language to describe the operations of digital circuits.

7. Name two types of HDLs.

·         Verilog

·         VHDL: Very High Speed Integrated Circuits Hardware Description Language.

8. What is module?

·         A module is the description of a unit that performs some function.

·         The basic unit of description in verilog.

·         It describes the functionality or structure of a design.

·         It describes the ports through which it communicates with other modules.

9. What is the difference between initial and always statement?

·         Initial statement: It executes only once.

·         Always statement: It executes in a loop i.e. it is executed repeatedly.

10. What is inter-statement delay?

·         Inter-statement delay: The delay by which a statement’s execution is delayed.

·         Example:       sum = (A^B)^C;

#4 carry = A&B + A&C + B&C;

·         The delay in the second statement specifies that the execution of the assignment is to be delayed by 4 time units, and then executes the second assignment.

11. What is intra-statement delay?

·         Intra-statement delay: The delay between computing the value of the right-hand side expression and its assignment to the left-hand side.

·         Example:       Sum = #3 (A^B)^C;

·         The delay in this statement means that the value of the RHS expression is to be computed first, wait for 3 time units, and then assign the value to the sum

12. List any two capabilities of verilog.

·         Primitive logic gates such as AND, OR & NAND are built-in into the language.

·         Flexibility of creating a user-defined primitive (UDP). This UDP can be either combinational or sequential logic primitive.

13. What are the types of event control?

·         Regular event control (edge-triggered )

·         Named event control

·         Event OR control

·         Level-sensitive timing control

14. What is value set?

·         Verilog supports four values to model the functionality of real hardware.

Value levels	Conditions in hardware circuit
0 1 x z	Logic 0, false Logic 1, true Unknown value High impedance

15. Define net.

·         Net is a data type that represents a physical connection between structural elements.

·         Its value is determined from the value of its drivers.

·         The default value to a net is Z.

·         Nets are declared with the keyword wire.

·         It can be declared as scalar or vector.

16. Write the syntax for gate primitive instantiation.

Gate_name instance_name (out, in_1, in_2, in_3, …….);

        Example: and g1 (c, a, b);

                     or g2 (c, a, b);

17. Define a port. How is it declared?

·         Ports are interface terminals that allow a module to communicate with other modules. These corresponds to the input and output points on a library cell.

·         All ports must be declared within a module lisiting.

·         Unidirectional port can be declared as

input in_1, in_2;

output out_1, out_2;

·         Bidirectional port can be declared as

inout IO_1, IO_2;

18. Define an identifier.

·         Identifiers are names of modules, variables, and other objects that can be used in the design.

·         Identifiers consist of upper & lower case letters, digits 0 through 9, the underscore character( _ ) and the dollar sign ($).

·         The first character must be a letter.

19. What is UDP?

·         User Defined Primitives are self-contained and do not instantiate other modules or primitives.

·         UDP declaration: primitive UDP_name (port list);

·         Two types of UDP: 1. Combinational

        2. Sequential

20. List the types of Gate delay

·         The signal propagation delay from any gate input to the gate output can be specified using a gate delay.

·         The gate delay can be specified in the gate instantiation itself.

·         Types of gate delay.

i.             rise delay

ii.            fall delay

iii.           turn-off delay

21. What are the types of structural modeling?

·         Switch instantiation (at the transistor level)

·         Gate instantiation (at the gate level)

·         Module instantiation (to create hierarchy)

·         UDP instantiation (at the gate level)

22. What are the types of procedural assignment?

(i) Blocking Procedural assignment:

·         A procedural assignment in which the assignment operator is an “=” is a blocking procedural assignment.

·         The assignment statement is executed before the next statement is executed.

·         Blocking assignment statements are executed in the order they are specified in a sequential block.

     (ii) Non-blocking procedural assignment:

·         In a non-blocking procedural assignment, the assignment symbol “<=” is used.

·         I t allow scheduling of assignment without blocking execution of the statements that follow in a sequential block.

23. What is the difference between reduction operator & bitwise operator?

·         Reduction Operator: It performs a bitwise operation on a single vector operand and yield a 1-bit result.

·         Bitwise Operator: It performs bitwise operation between two vector operands and yield vector result.

·         Example  A=4’b1010; B=4’b1101;

    Z=A&B = 4’b1000   --------------  Bitwise AND operation

    Z=&A=1’b0         ---------------- Reduction AND operation

24. What is replication operator?

·         Replication operator is used to concatenate the same number to the specified number of times.

·         Example: A=4’b1010; Z={ 2 {A}}=8’b1010 1010

·         In the above example, 2 is the replication constant that specifies how many times to replicate the 4-bit number A inside the bracket.

UNIT IV: CMOS CHIP DESIGN

1. Draw the symbols of N & P – switches.

Fig 1.2 pg 7 Weste

2. What is a crowbarred state.

In an inverter when both pull – up & pull down gates are simultaneously turned ON, a crowbarred state exists. This causes an indeterministic logic level and also causes static power to be dissipated. It is an unwanted condition.

3. Draw a CMOS NAND gate with its pull – up & pull – down Truth table.

Fig 1.6 Table 1.4 & table 1.5 pg 12 Weste.

4. Draw the symbol of a 2 i/p CMOS Mux.

Fig 1.11 Pg 18 Weste. Table 1.9 Pg 18

5. Draw  a CMOS positive level sensitive D latch.

Fig 1.12  Pg 19 Weste

6. What is 22V10?

·         22V10 is an industry standard PAL device.

·         Characteristics:   12 inputs,

10 I/Os,

24 pins

# Product terms: 9 10 12 14 16 14 12 10 8

·         I/O structure of 22V10 has a register, output 4:1 MUX, input 2:1 MUX and tristate buffer.

7. What is CLB?

·         CLB: Configurable Logic Blocks

·         CLB is a basic element (cell) in FPGA. 

·         CLB is used to implement different logic functions.

8. When is a full custom ASIC designed.?

     A full custom ASIC is designed if there is no suitable existing cell libraries available that can be used for the entire design or they are not fast enough or they consume too much power A  full custom ASIC is designed when the technology is new or very specialized.

9. What is a wafer lot?

     A wafer lot is a group of silicon wafers that are all processed together. Usually between 5 to 30 wafers are in a lot.

10. What is a mega cell.

     The standard  - cell areas may be used in combination with larger predesigned cells, such as microcontrollers, or microprocessors Which are called mega cells/megafunctions/system – level macros/ fixed  blocks/cores/functional standard blocks.

11. What is a gate array?

     In a gate array (GA) the transistors are predefined on the silicon wafer. The predefined pattern of transistors on a gate array is the base array and the smallest element that i9s replicated to make the base array is the base cell or primitive cell.

12.  What are the types of Masked gate arrays

·         Channeled gate array

·         Channelless gate array

·         Structured gate array.

13. List the features of Channeled gate array , Channelless gate array ,Structured gate array.

          Channeled gate array: a)Only interconnect is customized

                                      b)The interconnect uses predefined spaces between rows of

                                      base cells.

                                      c) Manufacturing lead time is between 2 days and 2 weeks.

          Channelless gate array : a) only some mask layers are customized

                                 b) Manufacturing lead time is between 2 days and 2 weeks.

                             c) No predefined  areas set aside for routing between cells.

          Structured gate array: a) Only interconnect is customized

                             b) Custom blocks can be embedded

                             c) Manufacturing lead time is between 2 days and 2 weeks.

14. List the features of PLD .

     No customized mask layers or logic cells

     Fast design turnaround

     A single large block of programmable interconnect

     A matrix of logic macrocells that usually consist of programmable array logic    followed by a flip – flop or latch.

15. What are the types of PLD’s.

     ROM, PROM, EPROM, EEPROM, UVPROM., Masked ROM, PAL, PLA etc.

16. Essential features of FPGA.

·         None of the mask layers are customized

·         Has a method for programming the basic logic cells & interconnect

·         The core is a regular array of programmable basic logic cells that can implement both combinational & sequential logic

·         A matrix of programmable interconnect surrounds the basic logic cells

·         Programmable I/o cells surround the core

·         Design turnaround is few hours.

UNIT V: CMOS TESTING

1. List some typical defects in the manufacturing of IC.
• Layer to layer shorts
• Discontinuous wires
• Thin – oxide shorts to substrate or well.
• Nodes shorted to ground or power
• Nodes shorted to each other
• Inputs floating
• Outputs disconnected
2. What are SA0 & SA1 faults.

When anode in a circuit is permanently at logic 1 or 0 due to thin oxide shorts , ie the n – transistor gate to Vss or the p – transistor gate to Vdd or meta to metal shorts. The SA0 or SA1 Fault occurs.

3. Define observability and controllability.

Observability: The observability of a particular internal circuit node is the degree to which one can observe that node at the outputs of an integrated circuit. Controllability : It is the measure of the ease of setting an  internal node to 1 or 0 state via primary inputs. A well designed circuit should have all nodes easily controllable.

4. What is fault sampling?

Fault sampling is one of the approaches to fault analysis. It is used in the circuit where it is impossible to fault every node in the circuit. In this approach, nodes are randomly selected and faulted.

5. What is a sensitized path?

In D – alg  one objective is to propagate a fault at a particular node to one or more primary o/p This path to the o/p pin is called a sensitized path.

6. What are primary i/p’s and o/p’s?

A primary output(Po) is adirectly observable signal ,such as a pad or a scan o/p .A primary input is one that can be directly set via a pad or some other means.

7. State the 3 types of fault simulation process.

1. Serial simulation 2. Parallel simulation  3. Concurrent simulation.

      8.    What is delay fault testing.

 In the case of a high powered NAND gate composed of paralleled n - & p –   

 transistors, if an open ckt occurs as in fig 7.10 pg 483 Weste  the gate would still 

 function but with increased pull down time. This is a delay fault.

9.   What is ILA testing.

An iterative logic array is a collection of identical logic modules . An ILA is C – testable if it can be tested with a constant number of input vectors independent of the iteration count. An ILA is I - testable if a particular fault that occurs in any module as a result of an applied input vector is identical for all modules in an ILA.

      10. What are the advantages & disadvantages of IDDQ.

As IDDQ is based on quiescent current measurement  which is time consuming, the tests must be run slower than normal ,thus increasing the test time. However this technique gives a form of indirect massive observability at little overhead.

       11. What are the various connections of a Test Access Port.(TAP).

                    The TAP has 4 or 5 single bit connections. They are

·         TCK(the test clock input) – used to clock tests into & out of chips.

·         TMS ( The test mode select) – used to control test operations.

·         TDI ( the test data input) – used to input test data to a chip.

·         TDO ( test data output) used to output test data from a chip.

It also has an optional signal

·         TRST( The test Reset Signal) used to synchronously reset the TAP controller: also used if a power – up reset signal is not available in the chip being tested.

12.  Describe the test architecture of a boundary scan  using TAP.

       Fig 7.25 pg 502 . Basic test architecture consists of

·         The TAP interface pins

·         A set of test data registers to collect datafrom chip

·         An instruction register to enable test inputs

·         A TAP controller, which interprets instructions & controls the flow of data.

13.What is a TAP controller.

The TAP controller is a 16 state FSM that proceeds from state to state based on TCK & TMS signals. It provides signals that control the test data registers & instruction registers.

14.Explain BYPASS ,EXTEST, SAMPLE /PRELOAD.

The instruction registers has to decode 3 instructions they are.

BYPASS – This instruction is represented by an IR having all zeroes in it. It is

used to bypass any serial data registers in a chip with a 1 – bit register. This

allows specifis chips to be tested in a serial scan scan chain without having to

shift through the accumulated SR  stages in all the chips.

EXTEST – This allows for the testing of off chip circuitry & is represnted by all ones in the IR.

SAMPLE /PRELOAD: - This instruction places the boundary scan register in the DR chain and samples or preloads the chip i/os.

15.What is a test DR.

The test data registers are used to set the inputs of modules to be tested and to collect the results of running tests.

16.What are boundary scan registers?

The boundary scan register is a special case of a data register. It allows circuit board interconnections to be tested, external components tested, and the state of chip digital I/Os to be sampled.