Electronics & Communication Engineering 7th semester notes

PART-A                                                                                 (10 x 2 = 20marks)

1. List any 4 advantages of SOI over n & p well processes.

·         Denser packing of devices is possible.

·         Lowered substrate capacitance – Faster ckts.

·         No latch – up as substrate is insulator.

·         Enhanced tolerance to radiation.

2. What is a LDD structure.

LDD stands for Lightly doped drain. It is a technology used to overcome hot electron effect. Initially the drain/source is lightly doped and over the gate a spacer oxide is grown over this a heavier implant is done, moving higher concentration of electrons away from gate.

3. Name 4 popular materials used as masks

Silicon di oxide

Photo resist

Poly - silicon

Silicon Nitride.

4. Name the two kinds of CMOS layout rules and give the minimum size for n- well layer in each of them.

Lamda rule - 10λ , Micron rule - 2µ.

5. Draw the ckt of a two input CMOS NAND gate.

6. What are the 2 kinds of delays in verilog statements?

1)      Inter statement

A= b + c;

#5 c = A + x;

2)      Intra statement

A = #5 b+c;

7. Construct a 2 x 1 MUX using tristate primitives.

A 2 X 1 MUX can be constructed using one bufif0 and one bufif1 as shown below.

8. Give the syntax of two conditional statements.

1)      if (expression) statement;

2)      if (expression) statement1;

else (expression) statement2;

3)      if (expression) statement1;

else if(expression) statement2;

else if(expression) statement3;

            ---

            ----

else default statement.

9. Explain the compiler directive  - timescale.

‘ timescale 1ns/100ps – is the syntax for this compiler directive . Here 1ns is the defined time unit and 100ps is the precision.

10. Define an identifier.

An identifier is a single group of characters which is used to reference the modules, objects and variables . It can be lower case and upper case alphabets, numbers from 0 to 9, $ (dollar) and _ (under score). It has to begin with a alphabet or under score. Verilog is case sensitive.

Set - II

PART-A                                                                                 (10 x 2 = 20marks)

1. Explain the different oxidation methods used in CMOS fabrication

a)      wet oxidation: Oxidizing the silicon wafer in the presence of water vapour between 900 C – 1000 C .This is a rapid process.

b)     Dry oxidation : Oxidizing the silicon wafer in the presence of oxygen around 1200 C . Acceptable growth rate.

2. List the advantages of twin tub over n / p- well processes.

·         Used for protection against latch-up

·         Provides separate optimization of p-type & n-type transistors

3. What are the different tools available in a typical CAD tool set?.

Design rule checker and Mask circuit – extraction program.

4. Draw the ckt of a CMOS 2 input NOR gate.

5. Define MSI, LSI and VLSI.

 MSl:Medium-scaleIntegration, 10<1000
 LSl:Large-scaleIntegration, Gates>1000
 VLSI: Very Large-scale Integration, Gates>100000

6. What is the difference between = = = and = = in Verilog ?

= = = is used for case equality and = =  is used for identity in Verilog HDL.

7. What is gate delay.

Verilog provides techniques for introducing delays at gate level.

The delay through agate is modeled using a single delay time – propagation delay

If rise time and fall time are known they are specified  as

nand # (t_rise,t_fall) G1( out,a,b );

Turn off delay can be specified as nand # (t_rise, t_fall, t_off) G1( out,a,b );

8. Give the symbol, Truth table and syntax of bufif1.

SYNTAX: bufif1 instance_name( out,in,ctrl);

      

		ctrl
		0	1	X	z
in	0	z	0	L	L
	1	z	1	H	H
	x	z	x	x	x
	z	z	x	x	x

                                                                          

9. Give the structural coding of a half adder.

module half (a,b,s,c);

input a;

input b;

output c;

output s;

xor (s,a,b);

and (c,a,b);

endmodule

10. Explain the significance of zero based delay.

Statements with # 0 delay are always executed last in the execution time step. This also avoids races.